A 3DIC is three dimensional integrated circuit. Which is build by vertically stacking different chips or wafers together into a single package. Within the package, the device is interconnect using through silicon vias or hybrid bonding.
With the huge demands for compute, allowing more processing in a tiny area at low power is must. By contrasting for 2D designs, more processing means an increase in clip area and power. 3D design or vertical integration, have emerged as a viable solution. In 2D ICs each die is package separately and laid out on a printed circuit board(PCB). Data transfer to and from stacked dies takes place through TVSs integrated in the bottom die. A 3DIC architecture increases functional density at the same or reduced power. The energy per bit transfer can be reduce to 30x with latest technology.
Reduced Cost and Footprint : Increasing the design sizes are causing major cost and yield problems expanding development cycles. This reverse the use of expensive nodes for only the critical parts of the system. And less expensive nodes for less critical parts. From the cost, a large system with different parts has various sweet spots in terms of silicon implementation.
Higher Bandwidth : Silicon designer want to integrate much functionality into the chip and deliver as high performance as possible. implementing 3D structure enable design to continue to add functionality to the product. There is always the required power and thermal envelopes.
Lower Power Consumption : Vertical stacking provide shorter and faster interconnect that reduce power consumption. 3DIC can yield the solution with greater capacity.
Heterogeneous Integration : It provides the opportunity to target to multiple end market applications through reuse. It provides flexibility, different manufacturing processes, technology nodes and even base technologies can be intermix.
Ideal Application for 3DIC
They are ideal for all kind of chips. The capacity and flexibility are ideal for compute intensive application. Such as high performance computing (HPC), data centers, cloud computing, artificial intelligence (AI) and machine learning (ML). The compact footprint is valuable for mobile devices, internet of things (IOT) and other applications where is at a premium.
It is the electronic design automation (EDA) industry only unified platform for end to end multi die design and integration within one package. It enables hundreds of thousands of inter die interconnects. it offers a full set of automated features along with power integrity. Provides single graphical user environment with 3D visualization. Supporting the exploration, design, implementation, validation, and signoff of 3DICs.
The die-to-die IP enables reliable 112G XSR and parallel-based HBI links, and the HBM IP allows up to 921 GB/s HBM3 SDRAMs. Designers are splitting SoCs into multiple dies to improve yield, PPA, and scalability for various use cases such as die splitting, die disaggregation, compute scaling and aggregation of functions.